1. Field of the Invention
The present invention relates to a method for synthesizing a clock signal, said signal being locked to a reference clock signal.
2. Description of the Prior Art
When developing digital communication systems, a condition is often faced where a clock signal of a desired frequency having frequency stability and low jitter has to be generated, deriving said signal from clock signals already available in the system and operating at preset frequencies, said clock signals being affected themselves by jitter.
The use of circuits based on closed loop circuits, in particular PLL circuits (Phase Locked Loop), represents the most widely employed solution for said problem.
However, though closed loop circuits are able to synthesize clock signals of a desired frequency with flexibility and good frequency features, they are expensive, bulky and high power consuming. This creates a hindrance to their integration in digital circuits.
On the other hand, manufacture of open loop circuits has the problem of efficiently compensating the jitter on the reference clock signal, avoiding to bring it to the output.
It is the object of the present invention to solve the above problems and provide a method for synthesizing a clock signal locked to a reference clock signal, having a more efficient and improved performance.
In this frame, it is the main object of the present invention to provide a method for synthesizing a clock signal locked to a reference clock signal, which has a simple implementation and is easily integrated in digital circuits.
A further object of the present invention is to provide a method for synthesizing a clock signal locked to a reference clock signal, through which a low jitter clock signal can be synthesized.
A further object of the present invention is to provide a method for synthesizing a clock signal locked to a reference clock signal, which has an open loop and, in particular, does not make use of PLL circuits.
A further object of the present invention is to provide a synthesizing device for digital clock signals ensuring the achievement of the method according to the present invention.
In order to achieve such objects, the present invention provides a method for synthesizing a clock signal locked to a reference clock signal and/or a synthesizing device for digital clock signals incorporating the features of the annexed claims, which form an integral part of the description herein.
Further objects, features and advantages of the present invention will become apparent from the following detailed description and annexed drawings, which are supplied by way of exemplifying and non limiting example.